The field of the present invention is integrated circuits in which a number of function elements are located in the semiconductor body. One problem in connection with the fabrication of integrated circuits lies in the provision of adequate means for isolating various function elements from each other except where electrical connections are required for the circuit. It is important also that the arrangement of the components of the integrated circuit be such that it minimizes production costs.
It is known that a substrate of one conductivity may have diffused in a surface portion thereof a heavily doped region of the opposite impurity type and to thereafter form an epitaxial layer of the opposite impurity type having relatively low doping on this substrate. The region of the opposite conductivity type which was initially diffused into the surface of the substrate then upwardly diffuses into a confronting portion of the epitaxial layer. This provides a heavily doped buried layer located partially in the substrate and partially in the epitaxial layer. Function elements can then be formed in the epitaxial layer adjacent the outer surface of the epitaxial layer. Such an arrangement is shown and described, for example, in Shannon, U.S. Pat. No. 3,761,319, issued Sept. 25, 1973.
In bipolar integrated circuits normally the function elements are electrically insulated from one another by special insulation-diffusion.
An integrated circuit of this type can, for example, be designed in such a manner that on to a p-doped substrate is deposited an n-type epitaxial layer whose surface is subsequently transformed into an oxide layer. Conventional photolithographic methods are used to etch frame-like structures into this oxide layer, through which a p.sup.+ diffusion (p.sup.+ indicates a high doping concentration) is effected to a depth at which the diffusion front overlaps with the p-doping of the substrate. In this way n-bodies are obtained which are entirely enclosed by a pn-junction. When the p-substrate and the p.sup.+ insulating frames are connected to the most negative potential, all the insulating-pn-junctions are poled in the blocking direction.
Depth diffusion inevitably involves a lateral diffusion beneath the oxide mask so that the subsequently diffused zones of the function elements, e.g., the p-base zones of npn-transistors, must always possess a sufficient distance from the insulating zone. This safety clearance is determined by the diffusion depths, adjustment tolerances and space charge zones. Therefore, the space requirement, for example of a transistor, is substantially dependent upon the area of space required for the insulation.
To avoid this disadvantage, the so-called isoplanar technique has become known. In this technique a thin silicon nitride layer is applied to the surface of the epitaxial layer and is structure-etched by means of known processes. The remaining nitride structures serve as mask for the etching of frame-like zones in the epitaxial layer with an etching depth of approximately half the thickness of the epitaxial layer. During a subsequent oxidation process, the exposed silicon in the etching trenches is locally transformed into silicon dioxide, the zones beneath the nitride layer remaining unaltered by the effects of the nitride, which latter has a masking action vis-a-vis oxygen. The oxidation is continued until the oxide boundary has passed the pn-junction between epitaxial layer and substrate. As a result, beneath the nitride remain islands which are insulated from the substrate by a pn-junction and form oxide frames with their lateral boundaries.
An insulation technique of this type offers the following advantages:
(a) The lateral dimensions of the silicon dioxide-insulating frames are comparable with or smaller than the corresponding widths of diffused p-frames in the diffusion-insulation technique. PA1 (b) The safety clearances between the diffusions (e.g., base and collector of a transistor) can theoretically be dispensed with, i.e., the diffusions can be taken right up to the oxide boundaries. In this case, adjustment tolerances are of no importance; PA1 (c) The side wall capacitances of the bodies are considerably reduced; PA1 (d) Photo lacquer--or mask errors which occur in the oxide-insulation zones are ineffective as a result of the greater oxide thickness. PA1 (a) The oxidation is limited to a technology with a small epitaxial thickness as otherwise the requisite oxide thicknesses and the times required for the production thereof become unviably great. PA1 (b) During the oxidation buried-layer zones which have diffused-in prior to the epitaxy usually are diffused into the epitaxial layer and accordingly impose a lower limit for the epitaxy thickness. PA1 (c) At the surface of the boundary between silicon/silicon dioxide round beads are formed, the height and shape of which are heavily dependent upon the oxide thickness and the profile of the trench etching. The topology at this "flat" surface represents a problem for the arrangement of conductor paths and generally speaking for the photo-lacquer layers in the planar process. PA1 (d) With the forms of doping conventionally employed for the substrate material, beneath the oxide of the insulating zones form inversion layers which render the insulation between individual bodies incomplete due to channel formation. Although this effect can be counteracted by increasing the substrate doping, this would in turn increase the base capacitance of the bodies.
These advantages are counteracted by a series of important disadvantages and problems: